There is a demand for an increase in the wiring density of a wiring layer in wiring substrates on which semiconductor chips are mountable. For example, a semi-additive process is used to form a high-density wiring layer. When wiring layers become higher in wiring density to reduce the interval between wiring patterns, there arises concern about a decrease in insulation reliability due to, for example, the occurrence of ion migration. Various measures have been taken to address such concern.
For example, to remove metal residues between wiring patterns considered as the cause of the occurrence of ion migration, the technique of removing a substrate surface between wiring patterns by etching is proposed. According to this technique, a depression is formed between wiring patterns by etching. (See, for example, Japanese Laid-open Patent Publication No. 2004-259774.)